In order to meet increasingly stringent requirements of high performance and cost effectiveness in the field of semiconductor memory devices, it is desirable to increase the integration level of semiconductor memory devices. In particular, the integration level of a semiconductor memory device is an important factor in determining the cost of a product. Since the integration level of a conventional two dimensional (2D) memory device is generally determined by an area occupied by a unit memory cell, it is considerably affected by micro patterning technology used to form the device. However, in order to achieve micro patterning, high-priced-equipment is typically required. Accordingly, attempts to increase the integration level of the conventional 2D memory device are being made continuously.
To overcome the limitation of 2D device structure, 3D semiconductor memory devices including memory cells arranged in a 3D manner have been proposed. However, for mass production of 3D semiconductor memory devices, a technology for achieving reliable products while reducing the cost per bit is desired.